Solid state Thin Film Batteries (TFB) are known to exhibit several advantages over conventional battery technology such as superior form factors, cycle life, power capability and safety. However, there is a need for cost effective and high-volume manufacturing (HVM) compatible fabrication technologies to enable broad market applicability of TFBs.
Past approaches to the patterning requirements for the TFB fabrication consisted of applying known methods of masking/patterning, such as photolithography and physical (shadow) masking. An example of the use of photolithography can be seen in an article published by W. C. West, et. al., in Journal of Micromech. and Microeng. (Vol. 12 (2002) 58-62). The use of physical (shadow) masking can be seen in many publications and patents, as implied by the schematic diagrams of the TFB process flows (see for example, U.S. Pat. No. 6,921,464 to Krasnov et. al. and U.S. Pat. No. 6,994,933 to Bates et. al.) and by their specific statements (see for an example, U.S. Pat. Pub. No. 2005-0079418A1 to Kelley et. al.). All of these use masking/patterning technology at every step of the fabrication process.
The traditional physical masking requirement leads to many disadvantages, especially related to HVM. For example, the use of physical masking will (1) add significant capital investment requirement for HVM and large area scaling, (2) increase cost of ownership (consumable mask cost, cleaning, chemicals, etc.), (3) decrease throughput because of alignment requirements, and (4) limit the substrate size and type (rigid, semi-rigid, or flexible), and thereby, limit the scaling for economy and cost reduction.
More particularly, in HVM processes, the use of physical masks (ubiquitous for traditional and current state-of-the-art TFB fabrication technologies) will contribute to higher complexity and higher cost in manufacturing. The complexity and cost result from the required fabrication of highly accurate masks and (automated) management systems for mask alignment and regeneration. Such cost and complexity can be inferred from well known photolithography processes used in the silicon-based integrated circuit industry. In addition, the cost results from the need for maintaining the masks as well as from throughput limitations by the added alignment steps. The adaptation becomes increasingly more difficult and costly as the manufacturing is scaled to larger area substrates for improved throughput and economies of scale (i.e., high volume manufacturing). Moreover, the scaling (to larger substrates) itself can be limited because of the limited availability and capability of the physical masks.
Another impact of the use of physical masking is the reduced utilization of a given substrate area, leading to non-optimal battery densities (charge, energy and power). This is so because of the fact that physical masks cannot completely limit the sputtered species from depositing underneath the masks, which in turn leads to some minimum non-overlap requirement between consecutive layers in order to maintain electrical isolation between key layers. The consequence of this minimum non-overlap requirement is the loss of cathode area, leading to overall loss of capacity, energy and power content of the TFB (when everything else is the same).
Yet another impact of the use of physical masking, in the typical integration schemes used previously, is the need for complex protective coatings to keep the anode (typically Li or Li-ion) from reacting with oxidants (O2, H2O, etc.) from the ambient. There are several patents that deal with such schemes (see for examples, U.S. Pat. No. 5,561,004 to Bates et al. and U.S. Pat. No. 6,916,679 to Snyder et al., for multi-layer coating and lamination, respectively).
And finally, processes that employ physical (shadow) masks typically suffer from particulate contamination, which ultimately impacts the yield.
Therefore, there remains a need for concepts and methods that can significantly reduce the cost by enabling simplified, more HVM-compatible TFB process technologies.